1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to sophisticated metallization systems including sensitive dielectric materials and lead-free bumps or metal pillars for connecting a chip to a package.
2. Description of the Related Art
Semiconductor devices, such as microprocessors, SRAMs, ASICs (application specific ICs), systems on chip (SoC) and the like, are typically formed on appropriate substrate materials, such as silicon and the like, wherein the individual integrated circuits are arranged in an array on a wafer so that most of the manufacturing steps, which may involve several hundred and more individual process steps in sophisticated integrated circuits, are performed simultaneously for all chip areas on the substrate, except for photolithography processes, metrology processes and packaging of the individual devices after dicing the substrate. Thus, economic constraints drive semiconductor manufacturers to steadily increase the substrate dimensions, thereby also increasing the area available for producing actual semiconductor devices and thus increasing production yield.
In addition to increasing the substrate area, it is also important to optimize the utilization of the substrate area for a given substrate size so as to actually use as much substrate area as possible for semiconductor devices and/or test structures that may be used for process control. In the attempt to maximize the useful surface area for a given substrate size, the feature sizes of circuit elements are steadily scaled down. Due to this ongoing demand for shrinking the feature sizes of highly sophisticated semiconductor devices, copper, in combination with low-k dielectric materials, has become a frequently used alternative for the formation of so-called interconnect structures comprising metal line layers and intermediate via layers that include metal lines as intra-layer connections and vias as inter-layer connections, which commonly connect individual circuit elements to provide the required functionality of the integrated circuit. Typically, a plurality of metal line layers and via layers stacked on top of each other is necessary to implement the connections between all internal circuit elements and I/O (input/output), power and ground pads of the circuit design under consideration.
For extremely scaled integrated circuits, the signal propagation delay is no longer limited by the circuit elements, such as field effect transistors and the like, but is limited, owing to the increased density of circuit elements requiring an even more increased number of electrical connections, by the close proximity of the metal lines, since the line-to-line capacitance is increased, in combination with a reduced conductivity of the lines due, to a reduced cross-sectional area. For this reason, traditional dielectrics such as silicon dioxide (k>4) and silicon nitride (k>7) are replaced by dielectric materials having a lower permittivity, which are, therefore, also referred to as low-k dielectrics, having a relative permittivity of 3 or less. However, the density and mechanical stability or strength of the low-k materials may be significantly less compared to the well-approved dielectrics silicon dioxide and silicon nitride. As a consequence, during the formation of the metallization system and any subsequent manufacturing processes of integrated circuits, production yield may depend on the mechanical characteristics of these sensitive dielectric materials and their adhesion to other materials.
In addition to the problems of reduced mechanical stabilities of advanced dielectric materials having a dielectric constant of 3.0 and significantly less, device reliability may be affected by these materials during the final assembly of sophisticated semiconductor devices, due to an interaction between the chip and the package caused by a thermal mismatch of the corresponding thermal expansion of the different materials. For instance, in the fabrication of complex integrated circuits, increasingly a contact technology may be used in connecting the package carrier to the chip, which is known as flip chip packaging technique. Contrary to the well-established wire bonding techniques in which appropriate contact pads may be positioned at the periphery of the very last metal layer of the chip, which may be connected to corresponding terminals of the package by a wire, in the flip chip technology, a respective bump structure may be formed on the last metallization layer, which may be brought into contact with respective contact pads of the package that have formed thereon a solder material. Thus, after reflowing the bump material, a reliable electrical and mechanical connection may be established between the terminal metal formed on the last metallization layer and the contact pads of the package carrier. In this manner, a very large number of electrical connections may be provided across the entire chip area of the last metallization layer with reduced contact resistance and parasitic capacitance, thereby providing the I/O (input/output) capabilities which may be required for complex integrated circuits, such as CPUs, storage memories and the like. During the corresponding process sequence for connecting the bump structure with a package carrier, a certain degree of pressure and heat may be applied to the composite device so as to establish a reliable connection between each of the bumps formed on the chip and the bumps or pads that may be provided on the package substrate. The thermally or mechanically induced stress may, however, also act on the lower lying metallization layers, which may typically include low-k dielectrics or even ultra low-k (ULK) dielectric materials, thereby significantly increasing the probability of creating defects in the form of cracks, delamination and the like, due to the reduced mechanical stability and adhesion to other materials.
In particular, one prominent failure mechanism is seen in the phase when the package substrate is actually connected to the semiconductor die by reflowing the solder material and subsequently solidifying the solder material so as to form an inter-metallic connection between the bump structure of the semiconductor die and the bump structure of the package substrate. In this process, the semiconductor die and the package substrate are mechanically coupled to each other and are heated above the melting temperature of the solder material, thereby reflowing the solder material and forming an inter-metallic connection. Thereafter, the composite device, i.e., the semiconductor die and the package substrate, are cooled down, which, however, may result in a pronounced yield loss, as will be explained in more detail with reference to FIGS. 1a-1j. 
FIG. 1a schematically illustrates a top view of a semiconductor die 150, which may be understood as a device comprising an appropriate carrier material, such as a silicon substrate, an insulating substrate and the like, in and above which circuit elements, such as transistors and the like, are provided. As discussed above, typically, the semiconductor die 150 comprises a metallization system including a plurality of metallization layers, when complex semiconductor devices are considered, in order to establish the connection between the individual semiconductor-based circuit elements. The metallization system (not shown) typically comprises a final metallization structure or contact structure 151, which comprises a plurality of contact elements, such as solder bumps, metal pillars and the like, which are to be connected to a complementary contact structure of a package substrate (not shown), as discussed above. The semiconductor die 150 may have any appropriate dimensions so as to accommodate one or more functional circuit portions, as required for obtaining the required operational behavior. As explained above, typically, the contact elements, such as the solder bumps, the metal pillars and the like, may be distributed across the entire surface area of the contact structure 151. Consequently, corresponding contact elements may typically be provided at any peripheral region 150P of the die 150 and also at a central region 150C.
FIG. 1b schematically illustrates an enlarged view of the peripheral region 150P, thereby schematically showing a plurality of contact elements 152, such as metal pillars in the form of copper pillars, solder bumps and the like, which may, in sophisticated applications, be provided in the form of a lead-free solder material and the like.
Similarly, FIG. 1c illustrates an enlarged view of the central region 150C, in which a plurality of solder bumps, metal pillars and the like 152 are provided in the contact structure 151. For example, in sophisticated applications, the lateral dimensions of the bumps or pillars 152 may be 100 um and less, depending on the I/O (input/output) requirements for corresponding circuits provided in the semiconductor die 150.
FIG. 1d schematically illustrates a cross-sectional view of a semiconductor device 100, which represents a composite semiconductor device comprising the semiconductor die 150 and a complementary package substrate 160. In the manufacturing stage shown, the die 150 and the package substrate 160 may be mechanically coupled by any appropriate external equipment (not shown), thereby mechanically connecting the bumps or pillars 152 of the contact structure 151 with complementary solder bumps 162 of a contact structure 161 of the package substrate 160. The package substrate 160 may comprise any appropriate inter-connect structure 165 in order to connect the various bumps 162 to any further contact features (not shown) for connecting the composite semiconductor device 100 with the periphery, for instance by contact pins, and the like. To this end, appropriate conductive lines (not shown) may connect to the various solder bumps 162 via appropriately configured contact pads 163.
Similarly, the semiconductor die 150 may comprise a substrate 156 including one or more semiconductor layers, in and above which circuit elements are formed (not shown), such as transistors, resistors, capacitors and the like. Furthermore, a metallization system 155 comprising a plurality of metallization layers (not shown) is typically formed “above” the substrate 156 and includes metal features, such as metal lines and vias, in order to establish the electrical connections between the individual circuit elements. As discussed above, the metallization system 155 may comprise sensitive low-k dielectric materials or ULK materials, in combination with highly conductive metals, such as copper, thereby resulting in a stack of metallization layers which may have a reduced mechanical strength. Consequently, any mechanical forces that may be exerted to the contact structure 151 may also be transferred to any lower-lying metallization layers of the system 155, thereby possibly creating severe damage therein, when the mechanical stress exceeds a certain magnitude.
The semiconductor die 150 may be formed on the basis of any well-established process strategy, in which sophisticated circuit elements, such as transistors having a critical dimension of 50 nm and less, may be provided in combination with a complex metallization system including a plurality of sensitive stacked metallization layers, which may receive as a final layer the contact structure 151 comprising any appropriate dielectric material in combination with the solder bumps or metal pillars 152. Generally, due to the ongoing demand for avoiding critical materials in semiconductor processing, such as lead, solder materials have been developed, for instance on the basis of silver, tin, copper and the like, in an attempt to avoid the usage of lead, wherein, however, these solder materials may generally have different mechanical characteristics and may typically have a higher melting point compared to lead-based solder materials. For example, lead-free solder materials are typically stiffer compared to the relatively soft lead-containing solder materials. Consequently, upon applying mechanical forces to the contact structure 151, a lead-free solder material or any other bump material may transfer resulting mechanical forces more efficiently into the underlying metallization system 155. Similarly, frequently, copper pillars may be used, which may even have a further increased stiffness, which may thus result in an increased mechanical stress in the vicinity of the contact features 152.
After separating the individual semiconductor die 150, the processing is continued by attaching the package substrate 160 to the die 150 and applying heat and a certain mechanical force in order to establish an inter-metallic connection between the bumps 152 of the die 150 and the bumps 162 of the package substrate 160. To this end, the composite device 100 is heated above the melting temperature of the solder material, such as the solder bumps 162, wherein, as discussed above, generally an increased temperature may be required compared to well-established lead-containing solder materials.
FIG. 1e schematically illustrates the device 100 during a first process phase in forming the desired inter-metallic connection between the various structures of the die 150 and the substrate 160 (FIG. 1d). For this purpose, a heat treatment 110 may be performed, in which the device 100 is heated to a temperature T that is higher than a melting temperature Tmelt of the solder material, wherein, typically, the device 100 is brought into an equilibrium state, i.e., substantially the same temperature is obtained at any position within the device 100 in order to initiate the reflowing of the solder material for any solder bump in the device 100. To this end, the device 100 may be efficiently thermally coupled to a process ambient, as indicated by 110, in which the device 100 may be uniformly heated, for instance by adjusting an appropriate process temperature within a process chamber accommodating the device 100. For example, appropriate heat media, such as gases and the like, may be appropriately supplied to the device 100 in order to obtain a uniform temperature across the entire volume of the device 100. Consequently, in this heating step, thermal energy may flow from any external temperature reservoir to the device 100, as indicated by the arrows in FIG. 1e. After achieving the desired reflow temperature, the temperature may be held constant for a certain time interval so as to establish appropriate process conditions for reflowing the solder material and forming the inter-metallic connection for any of the solder bumps. The status of substantially constant temperature above the melting temperature of the solder bump is indicated in FIG. 1e by the hatched surface of the device 100.
FIG. 1f schematically illustrates a diagram, in which the temperature of the device 100 is illustrated in the vertical axis, while the process time is shown on the horizontal axis. Thus, the phase 110 may thus comprise an interval of a rising temperature so as to finally reach the desired process temperature T, which may then be held constant for a desired time so as to achieve an equilibrium temperature for any point of the device 100 and to reliably establish the inter-metallic connection upon reflowing the solder material. It should be appreciated that the local temperature in the device 100 may vary prior to reaching the equilibrium state, since, for instance, peripheral areas may heat up faster than central areas, depending on the interaction between the process ambient and the device 100 during the process phase 110. Subsequent to the phase 110, the device 100 may be cooled down (process phase 111), which may be accomplished by changing the process temperature of the temperature reservoir, for instance by providing a heat medium of reduced temperature, by simply deactivating any heating elements and the like.
FIG. 1g schematically illustrates the qualitative progression of the temperature during a cooling phase 111, wherein the speed of temperature change may be selected in accordance with throughput criteria and overall thermal stress, which may build up upon heating or cooling the device 100 with increased speed. It turns out, however, that well-established process strategies for heating and, in particular, cooling the device 100 may result in increased yield losses upon using lead-free solder materials, pillar structures in the semiconductor die in combination with sophisticated metallization systems based on low-k dielectric materials. Without intending to restrict the present application to the following explanation, it is assumed that an increased internal temperature gradient may cause significant failures in the metallization systems due to an increased mechanical stress applied to the contact elements at peripheral areas of the semiconductor die.
FIG. 1h schematically illustrates the device 100 during the cooling phase 111, wherein the device 100 transfers heat energy to the process ambient, as indicated by the arrows in FIG. 1h. Since the peripheral area 100P of the device 100 may be coupled more intensively to the process ambient, for instance due to the overall increased surface area for a given volume compared to a central area 100C, the temperature at the peripheral area 100P, indicated as TP, may change faster and may thus be less than the temperature TC of the central area 100C. Consequently, the solder material in the peripheral area 100P may solidify earlier and may thus establish a strong mechanical connection between the semiconductor die and the package substrate, wherein, generally, the difference in the coefficient of thermal expansion between the substrate and the semiconductor die may additionally contribute to a corresponding mechanical stress, which may thus be transferred into the sensitive metallization system of the semiconductor die in the peripheral area 100P.
FIG. 1i schematically illustrates the device 100 in a further advanced phase of the cooling process 111, wherein the average temperature of the device 100 may be less compared to the average temperature as shown in FIG. 1h, while at the same time significant temperature gradient, indicated as TG, may have built up between the central region 100C and the peripheral region 100P, thereby even further increasing the mechanical stress, in particular in the central region 100P, in which the solder bumps may have been solidified for a longer time interval compared to any inner areas of the device 100.
FIG. 1j schematically illustrates a cross-sectional view of the device 100 in an advanced stage of the cooling phase 111 (FIG. 1i), wherein an inter-metallic connection between the contact features 152 and the bumps 162 is achieved, at least in the peripheral area 100P, wherein the significant temperature gradient TG may thus result in significant stress components 155C, 155T in the form of compressive and tensile stress in the vicinity of the contact features 152, since these features are generally less resilient compared to lead-containing solder bumps, as discussed above. Consequently, the significant stress components 155T, 155C may result in significant damage in the metallization system 155, for instance by inducing cracks and delamination 155S, in particular in sensitive low-k dielectric materials.
In some conventional approaches, the metallization system 155 is provided with superior mechanical characteristics, for instance by using harder and stiffer dielectric materials, which, in turn, may result in an increased permittivity and thus higher parasitic capacitance values, which may therefore lead to a significantly reduced electrical performance of the metallization system 155. Furthermore, using lead-containing solder materials may not be a viable solution in view of environmental aspects. Furthermore, a significant reduction of the temperature change during the cooling phase may result in a significant reduction of the overall process throughput, which may be less than desirable in volume production strategies.
The present disclosure is directed to various methods and systems that may avoid, or at least reduce, the effects of one or more of the problems identified above.